The present invention relates to an image processing technique, and particularly to an image processing technique capable of effectively using a plurality of image processors.
For a purpose of speeding up an image process, such process in the past has been performed so that it can be distributed to a plurality of image processors. As a method of distributing the process, a so-called pipeline architecture has been known so that the process can be divided into a plurality of stages, and data is sent to a subsequent stage at every end of the process for each divided stage. This architecture has been disclosed in Japanese Patent N. 3335482 and JP-A-2006-133839.
In the case of pipeline architecture, there is an idea to perform a data delivery/receipt between the stages effectively. The Japanese Patent No. 3335482 facilitates an enhancement of a processing efficiency by varying a connection between an image processor and an image line memory. The JP-A-2006-133839 also facilitates an enhancement of a processing efficiency by providing a dual-port memory between image processors.
Generally speaking, in the case of the pipeline process in the image process, the pipeline process includes an architecture which hands a process over to a subsequent stage at a time of completing the process for one-screen data amount. However, the pipeline process in the present invention means that a process is handed over to a subsequent stage before completing the process for the one-screen data amount.
That is, in the former case, one image processor accesses the one-screen data amount exclusively. In the latter case (present invention), a plurality of image processors sometimes access the one-screen data amount at a time.